Intel SOC Pre-Silicon Chip Design Firmware Engineer

Role Overview: Worked with architects and design engineers to generate micro-architecture and verification plans for power systems architecture for Intel’s 11th Generation Core Processors (Rocket Lake - Desktop and Tiger Lake - Mobile). Collaborated with architects to define and implement the handshake logic between IP and SOC and integrated them. Collaborated with design team to develop a detailed verification test-plan and support simulation bring-up, debug and bug fixes. Debugged, fixed, and validated pre- and post-silicon sub-system logic issues and bugs. Engineered a robust internal tool that took important data and generated useful validation collateral, assembly code, and documentation, all while ensuring compliance with industry standards. Validated power systems features written in assembly code, maintaining high (>95%) test coverage and low (<5%) bug escapes. Ran workshops for teams up to 15 to learn and implement new methodologies such as Agile, collaborative programming, and Clean Code, improving efficiency and quality of all code.

My Role: SOC Pre-Silicon Chip Design Firmware Engineer

Programming Languages: Assembly, Ruby

Role Duration: 3 Years (July 2016 - August 2019)